Messages in this thread | | | From | "Rafael J. Wysocki" <> | Date | Fri, 1 Oct 2021 20:46:17 +0200 | Subject | Re: [RESEND PATCH] x86: ACPI: cstate: Optimize C3 entry on AMD CPUs |
| |
On Sun, Sep 26, 2021 at 5:13 PM Thomas Gleixner <tglx@linutronix.de> wrote: > > On Fri, Sep 24 2021 at 18:48, Rafael J. Wysocki wrote: > > > On Fri, Sep 24, 2021 at 8:12 AM Deepak Sharma <deepak.sharma@amd.com> wrote: > >> > >> All Zen or newer CPU which support C3 shares cache. Its not necessary to > >> flush the caches in software before entering C3. This will cause drop in > >> performance for the cores which share some caches. ARB_DIS is not used > >> with current AMD C state implementation. So set related flags correctly. > >> > >> Signed-off-by: Deepak Sharma <deepak.sharma@amd.com> > > > > I'm planning to take this one unless the x86 maintainers have concerns, thanks. > > Acked-by: Thomas Gleixner <tglx@linutronix.de>
Thanks!
Applied as 5.16 material, thanks!
| |