Messages in this thread | | | Date | Fri, 08 Jan 2021 19:35:33 +0530 | From | Sai Prakash Ranjan <> | Subject | Re: [PATCH] drm/msm: Only enable A6xx LLCC code on A6xx |
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On 2021-01-08 19:09, Konrad Dybcio wrote: >> Konrad, can you please test this below change without your change? > > This brings no difference, a BUG still happens. We're still calling > to_a6xx_gpu on ANY device that's probed! Too bad it won't turn my A330 > into an A640.. > > Also, relying on disabling LLCC in the config is out of question as it > makes the arm32 kernel not compile with DRM/MSM and it just removes > the functionality on devices with a6xx.. (unless somebody removes the > dependency on it, which in my opinion is even worse and will cause > more problems for developers!). >
Disabling LLCC is not the suggestion, I was under the impression that was the cause here for the smmu bug. Anyways, the check for llc slice in case llcc is disabled is not correct as well. I will send a patch for that as well.
> The bigger question is how and why did that piece of code ever make it > to adreno_gpu.c and not a6xx_gpu.c? >
My mistake, I will move it.
> To solve it in a cleaner way I propose to move it to an a6xx-specific > file, or if it's going to be used with next-gen GPUs, perhaps manage > calling of this code via an adreno quirk/feature in adreno_device.c. > Now that I think about it, A5xx GPMU en/disable could probably managed > like that, instead of using tons of if-statements for each GPU model > that has it.. > > While we're at it, do ALL (and I truly do mean ALL, including the > low-end ones, this will be important later on) A6xx GPUs make use of > that feature? >
I do not have a list of all A6XX GPUs with me currently, but from what I know, A618, A630, A640, A650 has the support.
Thanks, Sai
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