Messages in this thread Patch in this message | | | From | Zhiqiang Hou <> | Subject | [PATCHv3 3/7] dt-bindings: pci: layerscape-pci: Add a optional property big-endian | Date | Fri, 8 Jan 2021 17:36:06 +0800 |
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From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
This property is to indicate the endianness when accessing the PEX_LUT and PF register block, so if these registers are implemented in big-endian, specify this property.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Acked-by: Rob Herring <robh@kernel.org> --- V3: - Rebased against the latest code base
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index daa99f7d4c3f..0033c898976e 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -39,6 +39,10 @@ Required properties: of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly. +Optional properties: +- big-endian: If the PEX_LUT and PF register block is in big-endian, specify + this property. + Example: pcie@3400000 { -- 2.17.1
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