Messages in this thread Patch in this message | | | From | Martin Blumenstingl <> | Subject | [PATCH 1/5] clk: meson: meson8b: don't use MPLL1 as parent of vclk_in_sel | Date | Mon, 4 Jan 2021 14:28:02 +0100 |
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MPLL1 is needed for audio output. Drop it from the vclk_in_sel parent list so we only use the (mutable) vid_pll_final_div tree or one of the (fixed) FCLK_DIV{3,4,5} clocks.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> --- drivers/clk/meson/meson8b.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index a844d35b553a..f8bd211db720 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -1154,6 +1154,10 @@ static struct clk_regmap meson8b_vid_pll_final_div = { }, }; +/* + * parent 0x6 is meson8b_mpll1 but we don't use it here because it's reserved + * for the audio outputs. + */ static const struct clk_hw *meson8b_vclk_mux_parent_hws[] = { &meson8b_vid_pll_final_div.hw, &meson8b_fclk_div4.hw, @@ -1161,7 +1165,6 @@ static const struct clk_hw *meson8b_vclk_mux_parent_hws[] = { &meson8b_fclk_div5.hw, &meson8b_vid_pll_final_div.hw, &meson8b_fclk_div7.hw, - &meson8b_mpll1.hw, }; static struct clk_regmap meson8b_vclk_in_sel = { -- 2.30.0
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