Messages in this thread | | | From | Thomas Gleixner <> | Subject | RE: [PATCH v4 1/4] x86/cpufeatures: Enumerate #DB for bus lock detection | Date | Thu, 28 Jan 2021 00:23:37 +0100 |
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Fenghua,
On Wed, Jan 27 2021 at 22:39, Fenghua Yu wrote: >> On Wed, Jan 27, 2021 2:16 PM, Thomas Gleixner wrote: >> On Tue, Nov 24 2020 at 20:52, Fenghua Yu wrote: >> >> > A bus lock is acquired though either split locked access to writeback >> > (WB) memory or any locked access to non-WB memory. This is typically >> > >1000 cycles slower than an atomic operation within a cache line. It >> > also disrupts performance on other cores. >> > >> > Some CPUs have ability to notify the kernel by an #DB trap after a >> > user instruction acquires a bus lock and is executed. This allows the >> > kernel to enforce user application throttling or mitigations. >> >> That's nice, but how does that interact with a data breakpoint on the same >> location? > > If both data breakpoint and bus lock happen on the same location, the bus lock > is handled first and then the data breakpoint is handled in the same exception: > > 1. If warn on bus lock, a rate limited warning is printed for the bus lock and then > a SIGTRAP is sent to the user process. > 2. If fatal on bus lock, a SIGBUS is sent to the user process for the bus lock and a > SIGTRAP is also sent to the user process. I think the SIGBUS will be delivered first > to the process and then SIGTRAP will be delivered to the process. > 3. If ratelimit on bus lock, first the tasks in the user sleep for specified time, then > SIGTRAP is sent to the user process. > > Is the interaction OK?
The ordering is a software choice and fine with me as long as the hardware actually delivers both.
All of this information needs to be in the changelog of the relevant patches.
Thanks,
tglx
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