Messages in this thread Patch in this message | | | From | Alexandru Ardelean <> | Subject | [PATCH v2 1/3] clk: axi-clkgen: remove ARCH dependency in Kconfig | Date | Tue, 26 Jan 2021 13:08:24 +0200 |
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The intent is to be able to run this driver to access the IP core in setups where FPGA board is also connected via a PCIe bus. In such cases the number of combinations explodes, where the host system can be an x86 with Xilinx Zynq/ZynqMP/Microblaze board connected via PCIe. Or even a ZynqMP board with a ZynqMP/Zynq/Microblaze connected via PCIe.
To accommodate for these cases, this change removes the limitation for this driver to be compilable only on Zynq/Microblaze architectures.
Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> --- drivers/clk/Kconfig | 1 - 1 file changed, 1 deletion(-)
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 85856cff506c..d8c2d4593926 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -247,7 +247,6 @@ config CLK_TWL6040 config COMMON_CLK_AXI_CLKGEN tristate "AXI clkgen driver" - depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST help Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx FPGAs. It is commonly used in Analog Devices' reference designs. -- 2.17.1
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