Messages in this thread Patch in this message | | | Date | Mon, 25 Jan 2021 11:42:49 -0700 | From | Mathieu Poirier <> | Subject | Re: [PATCH v7 03/28] coresight: Introduce device access abstraction |
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On Sun, Jan 10, 2021 at 10:48:25PM +0000, Suzuki K Poulose wrote: > We are about to introduce support for sysreg access to ETMv4.4+ > component. Since there are generic routines that access the > registers (e.g, CS_LOCK/UNLOCK , claim/disclaim operations, timeout) > and in order to preserve the logic of these operations at a > single place we introduce an abstraction layer for the accesses > to a given device. > > Cc: Mike Leach <mike.leach@linaro.org> > Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> > --- > Change since v6: > - Fix code indentation in coresight.h (Mathieu Poirier) > Change since v3 > - Dropped csa argument to read()/write(). > - Addressed comments on spacing and adding labels for the #if #else #endifs. > (Mathieu) > --- > drivers/hwtracing/coresight/coresight-catu.c | 1 + > drivers/hwtracing/coresight/coresight-core.c | 43 ++++ > .../hwtracing/coresight/coresight-cti-core.c | 1 + > drivers/hwtracing/coresight/coresight-etb10.c | 1 + > .../coresight/coresight-etm3x-core.c | 1 + > .../coresight/coresight-etm4x-core.c | 1 + > .../hwtracing/coresight/coresight-funnel.c | 1 + > .../coresight/coresight-replicator.c | 1 + > drivers/hwtracing/coresight/coresight-stm.c | 1 + > .../hwtracing/coresight/coresight-tmc-core.c | 1 + > drivers/hwtracing/coresight/coresight-tpiu.c | 1 + > include/linux/coresight.h | 193 +++++++++++++++++- > 12 files changed, 243 insertions(+), 3 deletions(-)
[...]
> +u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset); > +u32 coresight_read32(struct coresight_device *csdev, u32 offset); > +void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset); > +void coresight_relaxed_write32(struct coresight_device *csdev, > + u32 val, > + u32 offset);
More stacking - I fixed it.
> +u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset); > +u64 coresight_read64(struct coresight_device *csdev, u32 offset); > +void coresight_relaxed_write64(struct coresight_device *csdev, > + u64 val, u32 offset); > +void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset); > + > + > #else > static inline struct coresight_device * > coresight_register(struct coresight_desc *desc) { return NULL; } > @@ -369,10 +512,54 @@ static inline bool coresight_loses_context_with_cpu(struct device *dev) > { > return false; > } > -#endif > + > +static inline u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset) > +{ > + WARN_ON_ONCE(1); > + return 0; > +} > + > +static inline u32 coresight_read32(struct coresight_device *csdev, u32 offset) > +{ > + WARN_ON_ONCE(1); > + return 0; > +} > + > +static inline void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset) > +{ > +} > + > +static inline void coresight_relaxed_write32(struct coresight_device *csdev, > + u32 val, u32 offset) > +{ > +} > + > +static inline u64 coresight_relaxed_read64(struct coresight_device *csdev, > + u32 offset) > +{ > + WARN_ON_ONCE(1); > + return 0; > +} > + > +static inline u64 coresight_read64(struct coresight_device *csdev, u32 offset) > +{ > + WARN_ON_ONCE(1); > + return 0; > +} > + > +static inline void coresight_relaxed_write64(struct coresight_device *csdev, > + u64 val, u32 offset) > +{ > +} > + > +static inline void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset) > +{ > +} > + > +#endif /* IS_ENABLED(CONFIG_CORESIGHT) */ > > extern int coresight_get_cpu(struct device *dev); > > struct coresight_platform_data *coresight_get_platform_data(struct device *dev); > > -#endif > +#endif /* _LINUX_COREISGHT_H */ > -- > 2.24.1 >
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