Messages in this thread | | | Date | Tue, 26 Jan 2021 18:25:33 -0800 | From | Jakub Kicinski <> | Subject | Re: [PATCH v2 net 1/1] net: fec: Fix temporary RMII clock reset on link up |
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On Mon, 25 Jan 2021 11:07:45 +0100 Laurent Badel wrote: > fec_restart() does a hard reset of the MAC module when the link status > changes to up. This temporarily resets the R_CNTRL register which controls > the MII mode of the ENET_OUT clock. In the case of RMII, the clock > frequency momentarily drops from 50MHz to 25MHz until the register is > reconfigured. Some link partners do not tolerate this glitch and > invalidate the link causing failure to establish a stable link when using > PHY polling mode. Since as per IEEE802.11 the criteria for link validity
I think you meant 802.3, fixed that up and applied, thanks!
> are PHY-specific, what the partner should tolerate cannot be assumed, so > avoid resetting the MII clock by using software reset instead of hardware > reset when the link is up. This is generally relevant only if the SoC > provides the clock to an external PHY and the PHY is configured for RMII.
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