Messages in this thread | | | Date | Tue, 26 Jan 2021 17:25:33 +0100 | From | Wolfram Sang <> | Subject | Re: [PATCH v2 4/4] dmaengine: rcar-dmac: Add support for R-Car V3U |
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On Mon, Jan 25, 2021 at 03:24:31PM +0100, Geert Uytterhoeven wrote: > The DMACs (both SYS-DMAC and RT-DMAC) on R-Car V3U differ slightly from > the DMACs on R-Car Gen2 and other R-Car Gen3 SoCs: > 1. The per-channel registers are located in a second register block. > Add support for mapping the second block, using the appropriate > offsets and stride. > 2. The common Channel Clear Register (DMACHCLR) was replaced by a > per-channel register. > Update rcar_dmac_chan_clear{,_all}() to handle this. > As rcar_dmac_init() needs to clear the status before the individual > channels are probed, channel index and base address initialization > are moved forward. > > Inspired by a patch in the BSP by Phong Hoang > <phong.hoang.wz@renesas.com>. > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Apporach looks good, didn't check the gory details. However, it still works fine with I2C + DMA on V3U, so:
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
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