lkml.org 
[lkml]   [2021]   [Jan]   [26]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH 5.10 047/199] riscv: Fix sifive serial driver
    Date
    From: Damien Le Moal <damien.lemoal@wdc.com>

    [ Upstream commit 1f1496a923b6ba16679074fe77100e1b53cdb880 ]

    Setup the port uartclk in sifive_serial_probe() so that the base baud
    rate is correctly printed during device probe instead of always showing
    "0". I.e. the probe message is changed from

    38000000.serial: ttySIF0 at MMIO 0x38000000 (irq = 1,
    base_baud = 0) is a SiFive UART v0

    to the correct:

    38000000.serial: ttySIF0 at MMIO 0x38000000 (irq = 1,
    base_baud = 115200) is a SiFive UART v0

    Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
    Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
    Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
    Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/tty/serial/sifive.c | 1 +
    1 file changed, 1 insertion(+)

    diff --git a/drivers/tty/serial/sifive.c b/drivers/tty/serial/sifive.c
    index 13eadcb8aec4e..214bf3086c68a 100644
    --- a/drivers/tty/serial/sifive.c
    +++ b/drivers/tty/serial/sifive.c
    @@ -999,6 +999,7 @@ static int sifive_serial_probe(struct platform_device *pdev)
    /* Set up clock divider */
    ssp->clkin_rate = clk_get_rate(ssp->clk);
    ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE;
    + ssp->port.uartclk = ssp->baud_rate * 16;
    __ssp_update_div(ssp);

    platform_set_drvdata(pdev, ssp);
    --
    2.27.0


    \
     
     \ /
      Last update: 2021-01-26 17:20    [W:2.814 / U:2.172 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site