Messages in this thread | | | From | Linus Walleij <> | Date | Fri, 22 Jan 2021 11:06:30 +0100 | Subject | Re: [PATCH net-next 2/2] drivers: net: dsa: mt7530: MT7530 optional GPIO support |
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On Tue, Jan 19, 2021 at 4:20 AM DENG Qingfang <dqfext@gmail.com> wrote: > On Mon, Jan 18, 2021 at 10:55 PM Linus Walleij <linus.walleij@linaro.org> wrote: > > > > So for offset 0..14 this becomes bits > > 0, 1, 2, 4, 5, 6, 8, 9, 10, 12 ... 18 > > > > What is the logic in this and is it what you intend? > > Yes. Bit 0..2 are phy 0's LED 0..2, bit 4..6 are phy 1's LED 0..2, etc.
OK add a comment and explain how the bits relate to each PHY and how the lines are arranged per-phy so it is crystal clear for people reading the driver.
Thanks! Linus Walleij
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