Messages in this thread | | | Date | Thu, 21 Jan 2021 18:22:37 +0000 | From | Will Deacon <> | Subject | Re: [RFC PATCH 3/7] arm64: mm: use nGnRnE instead of nGnRE on Apple processors |
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On Thu, Jan 21, 2021 at 06:15:06PM +0000, Marc Zyngier wrote: > On 2021-01-21 17:55, Will Deacon wrote: > > On Thu, Jan 21, 2021 at 04:25:54PM +0000, Marc Zyngier wrote: > > > On 2021-01-21 15:12, Mohamed Mediouni wrote: > > > > Please ignore that patch. > > > > > > > > It turns out that the PCIe controller on Apple M1 expects posted > > > > writes and so the memory range for it ought to be set nGnRE. > > > > So, we need to use nGnRnE for on-chip MMIO and nGnRE for PCIe BARs. > > > > > > > > The MAIR approach isn’t adequate for such a thing, so we’ll have to > > > > look elsewhere. > > > > > > Well, there isn't many alternative to having a memory type defined > > > in MAIR if you want to access your PCIe devices with specific > > > semantics. > > > > > > It probably means defining a memory type for PCI only, but: > > > - we only have a single free MT entry, and I'm not sure we can > > > afford to waste this on a specific platform (can we re-purpose > > > GRE instead?), > > > > We already have an nGnRnE MAIR for config space accesses. > > I'm confused. If M1 needs nGnRE for PCI, and overrides nGnRE to nE > for its in-SoC accesses, where does nGnRE goes? > > Or do you propose that it is the page tables that get a different > MT index?
Right, I'm just saying that we already have an nGnRnE MAIR configuration so there's no need to worry about running out of entries if we need both nGnRE and nGnRnE to co-exist. The nasty part is how to plumb this into the mappings only for on-chip MMIO; I guess either a new API or we get ioremap() to pick the memory type based on the address :/
Will
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