Messages in this thread Patch in this message | | | From | Michal Simek <> | Subject | [PATCH v2 02/12] arm64: dts: zynqmp: Add DT description for si5328 for zcu102/zcu106 | Date | Thu, 21 Jan 2021 11:26:50 +0100 |
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Origin DT binding just specify driver but wasn't aligned with DT binding which came later. Extend description for zcu102 and zcu106 to cover latest binding.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> ---
Changes in v2: None
.../boot/dts/xilinx/zynqmp-zcu102-revA.dts | 17 ++++++++++++++ .../boot/dts/xilinx/zynqmp-zcu106-revA.dts | 22 +++++++++++++++++++ 2 files changed, 39 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index f1255f635dfd..5ff7ab665374 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -132,6 +132,12 @@ ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; + + refhdmi: refhdmi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <114285000>; + }; }; &can1 { @@ -526,6 +532,17 @@ si5328: clock-generator@69 {/* SI5328 - u20 */ * interrupt-parent = <&>; * interrupts = <>; */ + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + clocks = <&refhdmi>; + clock-names = "xtal"; + clock-output-names = "si5328"; + + si5328_clk: clk0@0 { + reg = <0>; + clock-frequency = <27000000>; + }; }; }; /* 5 - 7 unconnected */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 6e9efe233838..7910ac125101 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -132,6 +132,12 @@ ina226-u75 { compatible = "iio-hwmon"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; + + refhdmi: refhdmi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <114285000>; + }; }; &can1 { @@ -520,6 +526,22 @@ i2c@4 { reg = <4>; si5328: clock-generator@69 {/* SI5328 - u20 */ reg = <0x69>; + /* + * Chip has interrupt present connected to PL + * interrupt-parent = <&>; + * interrupts = <>; + */ + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + clocks = <&refhdmi>; + clock-names = "xtal"; + clock-output-names = "si5328"; + + si5328_clk: clk0@0 { + reg = <0>; + clock-frequency = <27000000>; + }; }; }; i2c@5 { -- 2.30.0
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