Messages in this thread | | | Date | Wed, 20 Jan 2021 10:59:46 +0100 | From | Maxime Ripard <> | Subject | Re: [PATCH v3] clk: sunxi-ng: h6: Fix clock divider range on some clocks |
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On Mon, Jan 18, 2021 at 12:09:12AM +0000, Andre Przywara wrote: > While comparing clocks between the H6 and H616, some of the M factor > ranges were found to be wrong: the manual says they are only covering > two bits [1:0], but our code had "5" in the number-of-bits field. > > By writing 0xff into that register in U-Boot and via FEL, it could be > confirmed that bits [4:2] are indeed masked off, so the manual is right. > > Change to number of bits in the affected clock's description. > > Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU") > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
Applied, thanks Maxime [unhandled content-type:application/pgp-signature] | |