Messages in this thread | | | Subject | Re: [PATCH 2/2] net: dsa: lantiq_gswip: Fix GSWIP_MII_CFG(p) register access | From | Hauke Mehrtens <> | Date | Sun, 3 Jan 2021 02:36:30 +0100 |
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On 1/3/21 2:25 AM, Martin Blumenstingl wrote: > There is one GSWIP_MII_CFG register for each switch-port except the CPU > port. The register offset for the first port is 0x0, 0x02 for the > second, 0x04 for the third and so on. > > Update the driver to not only restrict the GSWIP_MII_CFG registers to > ports 0, 1 and 5. Handle ports 0..5 instead but skip the CPU port. This > means we are not overwriting the configuration for the third port (port > two since we start counting from zero) with the settings for the sixth > port (with number five) anymore. > > The GSWIP_MII_PCDU(p) registers are not updated because there's really > only three (one for each of the following ports: 0, 1, 5). > > Fixes: 14fceff4771e51 ("net: dsa: Add Lantiq / Intel DSA driver for vrx200") > Cc: stable@vger.kernel.org > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
> --- > drivers/net/dsa/lantiq_gswip.c | 23 ++++++----------------- > 1 file changed, 6 insertions(+), 17 deletions(-) > > diff --git a/drivers/net/dsa/lantiq_gswip.c b/drivers/net/dsa/lantiq_gswip.c > index 5d378c8026f0..4b36d89bec06 100644 > --- a/drivers/net/dsa/lantiq_gswip.c > +++ b/drivers/net/dsa/lantiq_gswip.c > @@ -92,9 +92,7 @@ > GSWIP_MDIO_PHY_FDUP_MASK) > > /* GSWIP MII Registers */ > -#define GSWIP_MII_CFG0 0x00 > -#define GSWIP_MII_CFG1 0x02 > -#define GSWIP_MII_CFG5 0x04 > +#define GSWIP_MII_CFGp(p) (0x2 * (p)) > #define GSWIP_MII_CFG_EN BIT(14) > #define GSWIP_MII_CFG_LDCLKDIS BIT(12) > #define GSWIP_MII_CFG_MODE_MIIP 0x0 > @@ -392,17 +390,9 @@ static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set, > static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set, > int port) > { > - switch (port) { > - case 0: > - gswip_mii_mask(priv, clear, set, GSWIP_MII_CFG0); > - break; > - case 1: > - gswip_mii_mask(priv, clear, set, GSWIP_MII_CFG1); > - break; > - case 5: > - gswip_mii_mask(priv, clear, set, GSWIP_MII_CFG5); > - break; > - } > + /* There's no MII_CFG register for the CPU port */ > + if (!dsa_is_cpu_port(priv->ds, port)) > + gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port)); > } > > static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set, > @@ -822,9 +812,8 @@ static int gswip_setup(struct dsa_switch *ds) > gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1); > > /* Disable the xMII link */ > - gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, 0); > - gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, 1); > - gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, 5); > + for (i = 0; i < priv->hw_info->max_ports; i++) > + gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, i); > > /* enable special tag insertion on cpu port */ > gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN, >
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