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    Subject[PATCH v2] clk: aspeed: Fix APLL calculate formula from ast2600-A2
    Date
    Starting from A2, the A-PLL calculation has changed. Use the
    existing formula for A0/A1 and the new formula for A2 onwards.

    Fixes: d3d04f6c330a ("clk: Add support for AST2600 SoC")
    Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
    ---
    drivers/clk/clk-ast2600.c | 37 +++++++++++++++++++++++++++----------
    1 file changed, 27 insertions(+), 10 deletions(-)

    diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c
    index bbacaccad554..8933bd1506b3 100644
    --- a/drivers/clk/clk-ast2600.c
    +++ b/drivers/clk/clk-ast2600.c
    @@ -17,7 +17,8 @@

    #define ASPEED_G6_NUM_CLKS 71

    -#define ASPEED_G6_SILICON_REV 0x004
    +#define ASPEED_G6_SILICON_REV 0x014
    +#define CHIP_REVISION_ID GENMASK(23, 16)

    #define ASPEED_G6_RESET_CTRL 0x040
    #define ASPEED_G6_RESET_CTRL2 0x050
    @@ -190,18 +191,34 @@ static struct clk_hw *ast2600_calc_pll(const char *name, u32 val)
    static struct clk_hw *ast2600_calc_apll(const char *name, u32 val)
    {
    unsigned int mult, div;
    + u32 chip_id = readl(scu_g6_base + ASPEED_G6_SILICON_REV);

    - if (val & BIT(20)) {
    - /* Pass through mode */
    - mult = div = 1;
    + if (((chip_id & CHIP_REVISION_ID) >> 16) >= 2) {
    + if (val & BIT(24)) {
    + /* Pass through mode */
    + mult = div = 1;
    + } else {
    + /* F = 25Mhz * [(m + 1) / (n + 1)] / (p + 1) */
    + u32 m = val & 0x1fff;
    + u32 n = (val >> 13) & 0x3f;
    + u32 p = (val >> 19) & 0xf;
    +
    + mult = (m + 1);
    + div = (n + 1) * (p + 1);
    + }
    } else {
    - /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */
    - u32 m = (val >> 5) & 0x3f;
    - u32 od = (val >> 4) & 0x1;
    - u32 n = val & 0xf;
    + if (val & BIT(20)) {
    + /* Pass through mode */
    + mult = div = 1;
    + } else {
    + /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */
    + u32 m = (val >> 5) & 0x3f;
    + u32 od = (val >> 4) & 0x1;
    + u32 n = val & 0xf;

    - mult = (2 - od) * (m + 2);
    - div = n + 1;
    + mult = (2 - od) * (m + 2);
    + div = n + 1;
    + }
    }
    return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
    mult, div);
    --
    2.17.1
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