Messages in this thread | | | From | "Zhang, Rui" <> | Subject | RE: [PATCH 2/3] perf/x86/rapl: Fix energy counter detection | Date | Sat, 16 Jan 2021 08:19:35 +0000 |
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> -----Original Message----- > From: Peter Zijlstra <peterz@infradead.org> > Sent: Saturday, January 16, 2021 4:03 AM > To: Zhang, Rui <rui.zhang@intel.com> > Cc: mingo@redhat.com; acme@kernel.org; mark.rutland@arm.com; > alexander.shishkin@linux.intel.com; jolsa@redhat.com; > namhyung@kernel.org; linux-kernel@vger.kernel.org; x86@kernel.org; > kan.liang@linux.intel.com; ak@linux.intel.com > Subject: Re: [PATCH 2/3] perf/x86/rapl: Fix energy counter detection > Importance: High > > On Fri, Jan 15, 2021 at 05:22:07PM +0800, Zhang Rui wrote: > > In the RAPL ENERGY_COUNTER MSR, only the lower 32bits represent the > > energy counter, and the higher 32bits are reserved. > > > > Add the MSR mask for these MSRs to fix a problem that the RAPL PMU > > events are added erroneously when higher 32bits contain non-zero value. > > Why would these high bits be non-zero?
On SPR platform, the high bits of Psys energy counter are reused for other purpose. High bits for other RAPL domains energy counters still return 0.
I didn't mention this because I thought this patch should be okay as a generic fix.
Thanks, rui
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