Messages in this thread | | | Date | Fri, 15 Jan 2021 16:14:04 +0100 | From | Thierry Reding <> | Subject | Re: [PATCH v2 4/5] clk: tegra: Halve SCLK rate on Tegra20 |
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On Tue, Jan 12, 2021 at 03:27:23PM +0300, Dmitry Osipenko wrote: > Higher SCLK rates on Tegra20 require high core voltage. The higher > clock rate may have a positive performance effect only for AHB DMA > transfers and AVP CPU, but both aren't used by upstream kernel at all. > Halve SCLK rate on Tegra20 in order to remove the high core voltage > requirement. > > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > drivers/clk/tegra/clk-tegra20.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-)
Acked-by: Thierry Reding <treding@nvidia.com> [unhandled content-type:application/pgp-signature] | |