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SubjectRe: [PATCH] mmc: sdhci-pci-gli: Enlarge ASPM L1 entry delay of GL9763E
On Thu, 14 Jan 2021 at 07:25, 陳建宏 <reniuschengl@gmail.com> wrote:
>
> > Ulf Hansson <ulf.hansson@linaro.org> 於 2021年1月13日 週三 下午6:53寫道:
> >
> > On Wed, 6 Jan 2021 at 10:27, Renius Chen <reniuschengl@gmail.com> wrote:
> > >
> > > The R/W performance of GL9763E is low with some platforms, which
> > > support ASPM mechanism, due to entering L1 state very frequently
> > > in R/W process. Enlarge its ASPM L1 entry delay to improve the
> > > R/W performance of GL9763E.
> >
> > What do you mean by frequently? In between a burst of request or
> > during a burst of request?
>
> GL9763E enters ASPM L1 state after a very short idle in default, even
> during a burst of request.

Okay, then it certainly makes sense to extend the idle period.

Would you mind extending the commit message with some of this
information, as I think it's useful.

>
> > I am thinking that this could have an effect on energy instead, but I
> > guess it's not always straightforward to decide what's most important.
> >
> > Anyway, what does it mean when you change to use 0x3FF? Are you
> > increasing the idle period? Then for how long?
>
> Yes, we considered that having high performance is more important than
> saving power during a burst of request.
> So we increased the idle period for 260us, by setting 0x3FF to the
> ASPM L1 entry delay bits of our vendor-specific register.
> Anyway, GL9763E can still enter ASPM L1 state by a longer idle.

Most mmc controllers that uses runtime PM autosuspend for the same
reasons, uses and idle period time of ~50us. 260us is in the same
ballpark, so I am fine with that, if that works for you.

However, can you please add a comment in the code (and preferably also
to the commit message) that 0x3FF means using a 260us idle period?

[...]

Kind regards
Uffe

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