Messages in this thread | | | From | Doug Anderson <> | Date | Tue, 8 Sep 2020 08:00:02 -0700 | Subject | Re: [PATCHv3] soc: qcom: llcc: Support chipsets that can write to llcc registers |
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Hi,
On Mon, Sep 7, 2020 at 10:36 PM Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> wrote: > > --- a/include/linux/soc/qcom/llcc-qcom.h > +++ b/include/linux/soc/qcom/llcc-qcom.h > @@ -73,6 +73,7 @@ struct llcc_edac_reg_data { > * @bitmap: Bit map to track the active slice ids > * @offsets: Pointer to the bank offsets array > * @ecc_irq: interrupt for llcc cache error detection and reporting > + * @need_llcc_config: check if llcc configuration is required > */ > struct llcc_drv_data { > struct regmap *regmap; > @@ -85,6 +86,7 @@ struct llcc_drv_data { > unsigned long *bitmap; > u32 *offsets; > int ecc_irq; > + bool need_llcc_config;
Do you really need to add this into "struct llcc_drv_data"? You use it once at probe time and you could just pass it in to qcom_llcc_cfg_program(), or just pass the "struct qcom_llcc_config" to qcom_llcc_cfg_program()? It's not a huge deal, but it would make your patch simpler and keep an extra element out of the include file.
In any case:
Reviewed-by: Douglas Anderson <dianders@chromium.org>
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