Messages in this thread | | | Date | Mon, 7 Sep 2020 18:58:51 +0200 | From | Borislav Petkov <> | Subject | Re: [PATCH v7 19/72] x86/boot/compressed/64: Add stage1 #VC handler |
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On Mon, Sep 07, 2020 at 03:15:20PM +0200, Joerg Roedel wrote: > +static inline u64 sev_es_rd_ghcb_msr(void) > +{ > + unsigned long low, high; > + > + asm volatile("rdmsr\n" : "=a" (low), "=d" (high) : > + "c" (MSR_AMD64_SEV_ES_GHCB)); > + > + return ((high << 32) | low); > +} > + > +static inline void sev_es_wr_ghcb_msr(u64 val) > +{ > + u32 low, high; > + > + low = val & 0xffffffffUL; > + high = val >> 32; > + > + asm volatile("wrmsr\n" : : "c" (MSR_AMD64_SEV_ES_GHCB), ^^
No need for that newline and the one above. I've zapped it while applying.
-- Regards/Gruss, Boris.
https://people.kernel.org/tglx/notes-about-netiquette
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