Messages in this thread | | | From | Anup Patel <> | Date | Mon, 7 Sep 2020 15:29:04 +0530 | Subject | Re: [PATCH] RISC-V: Allow drivers to provide custom read_cycles64 for M-mode kernel |
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On Mon, Sep 7, 2020 at 11:48 AM Christoph Hellwig <hch@lst.de> wrote: > > On Sat, Sep 05, 2020 at 11:05:48AM +0530, Anup Patel wrote: > > Your patch will also break if the SOC specific timer has a 32bit > > free-running counter > > unlike the 64bit free-running counter found on CLINT. > > > > I guess it's better to let the SOC timer driver provide the > > method/function to read the > > free-running counter. > > Seriously, build the interfaces once you know the consumers. Don't > build pie in the sky interfaces just because you can, because that > is what creates all the problems. > > And of coruse at least for IPIs which absolutely are performance > criticical we need a standard interface (one that doesn't suck as much > as the SBI detour with the four extra context switches). But I guess > I have already given up on RISC-V because the incompetency about things > like the irq design are just so horrible that it isn't worth bothering > any more.
Most of us are aware of these issues. The SBI IPI call will eventually become fallback option once we have standard mechanism for IPI in RISC-V privilege spec. Until then we try our best to support all existing RISC-V systems out there. This also means we end-up supporting existing SOC specific timers and IPI injection mechanisms.
Regards, Anup
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