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    Subject[PATCH v7 05/72] x86/cpufeatures: Add SEV-ES CPU feature
    Date
    From: Tom Lendacky <thomas.lendacky@amd.com>

    Add CPU feature detection for Secure Encrypted Virtualization with
    Encrypted State. This feature enhances SEV by also encrypting the
    guest register state, making it in-accessible to the hypervisor.

    Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
    Signed-off-by: Joerg Roedel <jroedel@suse.de>
    ---
    arch/x86/include/asm/cpufeatures.h | 1 +
    arch/x86/kernel/cpu/amd.c | 3 ++-
    arch/x86/kernel/cpu/scattered.c | 1 +
    3 files changed, 4 insertions(+), 1 deletion(-)

    diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
    index e1013056eb12..0f1da4a6e886 100644
    --- a/arch/x86/include/asm/cpufeatures.h
    +++ b/arch/x86/include/asm/cpufeatures.h
    @@ -236,6 +236,7 @@
    #define X86_FEATURE_EPT_AD ( 8*32+17) /* Intel Extended Page Table access-dirty bit */
    #define X86_FEATURE_VMCALL ( 8*32+18) /* "" Hypervisor supports the VMCALL instruction */
    #define X86_FEATURE_VMW_VMMCALL ( 8*32+19) /* "" VMware prefers VMMCALL hypercall instruction */
    +#define X86_FEATURE_SEV_ES ( 8*32+20) /* AMD Secure Encrypted Virtualization - Encrypted State */

    /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
    #define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/
    diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
    index dcc3d943c68f..6062ce586b95 100644
    --- a/arch/x86/kernel/cpu/amd.c
    +++ b/arch/x86/kernel/cpu/amd.c
    @@ -614,7 +614,7 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
    * If BIOS has not enabled SME then don't advertise the
    * SME feature (set in scattered.c).
    * For SEV: If BIOS has not enabled SEV then don't advertise the
    - * SEV feature (set in scattered.c).
    + * SEV and SEV_ES feature (set in scattered.c).
    *
    * In all cases, since support for SME and SEV requires long mode,
    * don't advertise the feature under CONFIG_X86_32.
    @@ -645,6 +645,7 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
    setup_clear_cpu_cap(X86_FEATURE_SME);
    clear_sev:
    setup_clear_cpu_cap(X86_FEATURE_SEV);
    + setup_clear_cpu_cap(X86_FEATURE_SEV_ES);
    }
    }

    diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
    index bccfc9ff3cc1..bf01a9693c6c 100644
    --- a/arch/x86/kernel/cpu/scattered.c
    +++ b/arch/x86/kernel/cpu/scattered.c
    @@ -42,6 +42,7 @@ static const struct cpuid_bit cpuid_bits[] = {
    { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 },
    { X86_FEATURE_SME, CPUID_EAX, 0, 0x8000001f, 0 },
    { X86_FEATURE_SEV, CPUID_EAX, 1, 0x8000001f, 0 },
    + { X86_FEATURE_SEV_ES, CPUID_EAX, 3, 0x8000001f, 0 },
    { 0, 0, 0, 0, 0 }
    };

    --
    2.28.0
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