Messages in this thread | | | Subject | Re: [PATCH 1/2] mips: Add strong UC ordering config | From | Jiaxun Yang <> | Date | Fri, 25 Sep 2020 11:54:20 +0800 |
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在 2020/9/20 19:00, Serge Semin 写道: > In accordance with [1, 2] memory transactions using CCA=2 (Uncached > Cacheability and Coherency Attribute) are always strongly ordered. This > means the younger memory accesses using CCA=2 are never allowed to be > executed before older memory accesses using CCA=2 (no bypassing is > allowed), and Loads and Stores using CCA=2 are never speculative. It is > expected by the specification that the rest of the system maintains these > properties for processor initiated uncached accesses. So the system IO > interconnect doesn't reorder uncached transactions once they have left the > processor subsystem. Taking into account these properties and what [3] > says about the relaxed IO-accessors we can infer that normal Loads and > Stores from/to CCA=2 memory and without any additional execution barriers > will fully comply with the {read,write}X_relaxed() methods requirements. > > Let's convert then currently generated relaxed IO-accessors to being pure > Loads and Stores. Seeing the commit 3d474dacae72 ("MIPS: Enforce strong > ordering for MMIO accessors") and commit 8b656253a7a4 ("MIPS: Provide > actually relaxed MMIO accessors") have already made a preparation in the > corresponding macro, we can do that just by replacing the "barrier" > parameter utilization with the "relax" one. Note the "barrier" macro > argument can be removed, since it isn't fully used anyway other than being > always assigned to 1. > > Of course it would be fullish to believe that all the available MIPS-based > CPUs completely follow the denoted specification, especially considering > how old the architecture is. Instead we introduced a dedicated kernel > config, which when enabled will convert the relaxed IO-accessors to being > pure Loads and Stores without any additional barriers around. So if some > CPU supports the strongly ordered UC memory access, it can enable that > config and use a fully optimized relaxed IO-methods. For instance, > Baikal-T1 architecture support code will do that. > > [1] MIPS Coherence Protocol Specification, Document Number: MD00605, > Revision 01.01. September 14, 2015, 4.2 Execution Order Behavior, > p. 33 > > [2] MIPS Coherence Protocol Specification, Document Number: MD00605, > Revision 01.01. September 14, 2015, 4.8.1 IO Device Access, p. 58 > > [3] "LINUX KERNEL MEMORY BARRIERS", Documentation/memory-barriers.txt, > Section "KERNEL I/O BARRIER EFFECTS" > > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> > Cc: Maciej W. Rozycki <macro@linux-mips.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Based on #mipslinus discussions, I suspect this option can be selected by most modern MIPS processors including all IMG/MTI cores, Ingenic and Loongson.
Thanks.
- Jiaxun
> --- > arch/mips/Kconfig | 8 ++++++++ > arch/mips/include/asm/io.h | 20 ++++++++++---------- > 2 files changed, 18 insertions(+), 10 deletions(-) >
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