| From | Greg Kroah-Hartman <> | Subject | [PATCH 4.9 58/70] MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT | Date | Mon, 21 Sep 2020 18:27:58 +0200 |
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From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
[ Upstream commit 564c836fd945a94b5dd46597d6b7adb464092650 ]
Commit 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>") forgot to select the correct MIPS_L1_CACHE_SHIFT for SNI RM. This breaks non coherent DMA because of a wrong allocation alignment.
Fixes: 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>") Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Sasha Levin <sashal@kernel.org> --- arch/mips/Kconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index f8a529c852795..24eb7fe7922e6 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -848,6 +848,7 @@ config SNI_RM select I8253 select I8259 select ISA + select MIPS_L1_CACHE_SHIFT_6 select SWAP_IO_SPACE if CPU_BIG_ENDIAN select SYS_HAS_CPU_R4X00 select SYS_HAS_CPU_R5000 -- 2.25.1
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