Messages in this thread | | | Date | Thu, 17 Sep 2020 11:41:26 +0200 | From | Thomas Bogendoerfer <> | Subject | Re: [PATCH] MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT |
| |
On Mon, Sep 14, 2020 at 06:05:00PM +0200, Thomas Bogendoerfer wrote: > Commit 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>") forgot > to select the correct MIPS_L1_CACHE_SHIFT for SNI RM. This breaks non > coherent DMA because of a wrong allocation alignment. > > Fixes: 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>") > Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> > --- > arch/mips/Kconfig | 1 + > 1 file changed, 1 insertion(+)
applied to mips-fixes.
Thomas.
-- Crap can work. Given enough thrust pigs will fly, but it's not necessarily a good idea. [ RFC1925, 2.3 ]
| |