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    Subject[PATCH AUTOSEL 4.14 092/127] arm64: cpufeature: Relax checks for AArch32 support at EL[0-2]
    Date
    From: Will Deacon <will@kernel.org>

    [ Upstream commit 98448cdfe7060dd5491bfbd3f7214ffe1395d58e ]

    We don't need to be quite as strict about mismatched AArch32 support,
    which is good because the friendly hardware folks have been busy
    mismatching this to their hearts' content.

    * We don't care about EL2 or EL3 (there are silly comments concerning
    the latter, so remove those)

    * EL1 support is gated by the ARM64_HAS_32BIT_EL1 capability and handled
    gracefully when a mismatch occurs

    * EL0 support is gated by the ARM64_HAS_32BIT_EL0 capability and handled
    gracefully when a mismatch occurs

    Relax the AArch32 checks to FTR_NONSTRICT.

    Tested-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
    Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
    Link: https://lore.kernel.org/r/20200421142922.18950-8-will@kernel.org
    Signed-off-by: Will Deacon <will@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    arch/arm64/kernel/cpufeature.c | 10 +++-------
    1 file changed, 3 insertions(+), 7 deletions(-)

    diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
    index 6b3bb67596ae8..b7d400a8921db 100644
    --- a/arch/arm64/kernel/cpufeature.c
    +++ b/arch/arm64/kernel/cpufeature.c
    @@ -136,11 +136,10 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
    ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
    S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
    S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
    - /* Linux doesn't care about the EL3 */
    ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
    - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
    - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
    - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
    + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
    + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
    + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
    ARM64_FTR_END,
    };

    @@ -627,9 +626,6 @@ void update_cpu_features(int cpu,
    taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
    info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);

    - /*
    - * EL3 is not our concern.
    - */
    taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
    info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
    taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
    --
    2.25.1
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