Messages in this thread | | | From | Florian Fainelli <> | Subject | Re: [PATCH v3 00/16] arm/arm64: Turning IPIs into normal interrupts | Date | Wed, 16 Sep 2020 09:54:17 -0700 |
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On 9/1/2020 7:43 AM, Marc Zyngier wrote: > For as long as SMP ARM has existed, IPIs have been handled as > something special. The arch code and the interrupt controller exchange > a couple of hooks (one to generate an IPI, another to handle it). > > Although this is perfectly manageable, it prevents the use of features > that we could use if IPIs were Linux IRQs (such as pseudo-NMIs). It > also means that each interrupt controller driver has to follow an > architecture-specific interface instead of just implementing the base > irqchip functionalities. The arch code also duplicates a number of > things that the core irq code already does (such as calling > set_irq_regs(), irq_enter()...). > > This series tries to remedy this on arm/arm64 by offering a new > registration interface where the irqchip gives the arch code a range > of interrupts to use for IPIs. The arch code requests these as normal > per-cpu interrupts. > > The bulk of the work is at the interrupt controller level, where all 5 > irqchips used on arm+SMP/arm64 get converted. > > Finally, we drop the legacy registration interface as well as the > custom statistics accounting. > > Note that I have had a look at providing a "generic" interface by > expanding the kernel/irq/ipi.c bag of helpers, but so far all > irqchips have very different requirements, so there is hardly anything > to consolidate for now. Maybe some as hip04 and the Marvell horror get > cleaned up (the latter certainly could do with a good dusting). > > This has been tested on a bunch of 32 and 64bit guests (GICv2, GICv3), > as well as 64bit bare metal (GICv3). The RPi part has only been tested > in QEMU as a 64bit guest, while the HiSi and Marvell parts have only > been compile-tested. > > I'm aiming for 5.10 for this, so any comment would be appreciated.
FWIW, I boot tested this on a Brahma-B53 device (GIC-400) in 32-bit and 64-bit mode and on a Brahma-B15 device (GIC-400 as well) and both devices worked in all 3 configurations:
Tested-by: Florian Fainelli <f.fainelli@gmail.com>
All cores were brought up successfully. All of these devices use PSCI/ATF FWIW. -- Florian
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