Messages in this thread Patch in this message | | | From | Mathieu Poirier <> | Subject | [PATCH 11/16] coresight: etm4x: Fix issues on trcseqevr access | Date | Wed, 16 Sep 2020 13:17:32 -0600 |
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From: Jonathan Zhou <jonathan.zhouwen@huawei.com>
The TRCSEQEVR(3) is reserved, using '@nrseqstate - 1' instead to avoid accessing the reserved register.
Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Shaokun Zhang <zhangshaokun@hisilicon.com> Cc: lizixian@hisilicon.com Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU low power states") Signed-off-by: Jonathan Zhou <jonathan.zhouwen@huawei.com> [Fixed capital letter in title] Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> --- drivers/hwtracing/coresight/coresight-etm4x.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 63cb1e0d5953..b29ad4f7fac2 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -1193,7 +1193,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) state->trcvdsacctlr = readl(drvdata->base + TRCVDSACCTLR); state->trcvdarcctlr = readl(drvdata->base + TRCVDARCCTLR); - for (i = 0; i < drvdata->nrseqstate; i++) + for (i = 0; i < drvdata->nrseqstate - 1; i++) state->trcseqevr[i] = readl(drvdata->base + TRCSEQEVRn(i)); state->trcseqrstevr = readl(drvdata->base + TRCSEQRSTEVR); @@ -1298,7 +1298,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) writel_relaxed(state->trcvdsacctlr, drvdata->base + TRCVDSACCTLR); writel_relaxed(state->trcvdarcctlr, drvdata->base + TRCVDARCCTLR); - for (i = 0; i < drvdata->nrseqstate; i++) + for (i = 0; i < drvdata->nrseqstate - 1; i++) writel_relaxed(state->trcseqevr[i], drvdata->base + TRCSEQEVRn(i)); -- 2.25.1
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