Messages in this thread Patch in this message | | | From | "Chia-Wei, Wang" <> | Subject | [PATCH 4/4] pinctrl: aspeed-g5: Fix LPC register offsets | Date | Fri, 11 Sep 2020 11:46:31 +0800 |
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The LPC register offsets are fixed to adapt to the LPC DTS change, where the LPC partitioning is removed.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> --- drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c index 0cab4c2576e2..98e62333fa54 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c @@ -60,7 +60,7 @@ #define COND2 { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 } /* LHCR0 is offset from the end of the H8S/2168-compatible registers */ -#define LHCR0 0x20 +#define LHCR0 0xa0 #define GFX064 0x64 #define B14 0 -- 2.17.1
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