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    SubjectRe: [PATCH 18/19] iommu/arm-smmu: add a way for implementations to influence SCTLR
    On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote:

    > From: Rob Clark <robdclark@chromium.org>
    >
    > For the Adreno GPU's SMMU, we want SCTLR.HUPCF set to ensure that
    > pending translations are not terminated on iova fault. Otherwise
    > a terminated CP read could hang the GPU by returning invalid
    > command-stream data.
    >

    Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

    > Signed-off-by: Rob Clark <robdclark@chromium.org>
    > ---
    > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 6 ++++++
    > drivers/iommu/arm/arm-smmu/arm-smmu.c | 3 +++
    > drivers/iommu/arm/arm-smmu/arm-smmu.h | 3 +++
    > 3 files changed, 12 insertions(+)
    >
    > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
    > index 5640d9960610..2aa6249050ff 100644
    > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
    > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
    > @@ -127,6 +127,12 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
    > (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64))
    > pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1;
    >
    > + /*
    > + * On the GPU device we want to process subsequent transactions after a
    > + * fault to keep the GPU from hanging
    > + */
    > + smmu_domain->cfg.sctlr_set |= ARM_SMMU_SCTLR_HUPCF;
    > +
    > /*
    > * Initialize private interface with GPU:
    > */
    > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c
    > index e63a480d7f71..bbec5793faf8 100644
    > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
    > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
    > @@ -617,6 +617,9 @@ void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx)
    > if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
    > reg |= ARM_SMMU_SCTLR_E;
    >
    > + reg |= cfg->sctlr_set;
    > + reg &= ~cfg->sctlr_clr;
    > +
    > arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg);
    > }
    >
    > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h
    > index cd75a33967bb..2df3a70a8a41 100644
    > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h
    > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h
    > @@ -144,6 +144,7 @@ enum arm_smmu_cbar_type {
    > #define ARM_SMMU_CB_SCTLR 0x0
    > #define ARM_SMMU_SCTLR_S1_ASIDPNE BIT(12)
    > #define ARM_SMMU_SCTLR_CFCFG BIT(7)
    > +#define ARM_SMMU_SCTLR_HUPCF BIT(8)
    > #define ARM_SMMU_SCTLR_CFIE BIT(6)
    > #define ARM_SMMU_SCTLR_CFRE BIT(5)
    > #define ARM_SMMU_SCTLR_E BIT(4)
    > @@ -341,6 +342,8 @@ struct arm_smmu_cfg {
    > u16 asid;
    > u16 vmid;
    > };
    > + u32 sctlr_set; /* extra bits to set in SCTLR */
    > + u32 sctlr_clr; /* bits to mask in SCTLR */
    > enum arm_smmu_cbar_type cbar;
    > enum arm_smmu_context_fmt fmt;
    > };
    > --
    > 2.26.2
    >

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