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    Subject[PATCH 15/18] spi: stm32: fix stm32_spi_prepare_mbr in case of odd clk_rate
    Date
    From: Amelie Delaunay <amelie.delaunay@st.com>

    Fix spi->clk_rate when it is odd to the nearest lowest even value because
    minimum SPI divider is 2.

    Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
    Signed-off-by: Alain Volmat <alain.volmat@st.com>
    ---
    drivers/spi/spi-stm32.c | 3 ++-
    1 file changed, 2 insertions(+), 1 deletion(-)

    diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
    index 0aec32538093..2665d8d7f318 100644
    --- a/drivers/spi/spi-stm32.c
    +++ b/drivers/spi/spi-stm32.c
    @@ -436,7 +436,8 @@ static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
    {
    u32 div, mbrdiv;

    - div = DIV_ROUND_UP(spi->clk_rate, speed_hz);
    + /* Ensure spi->clk_rate is even */
    + div = DIV_ROUND_UP(spi->clk_rate & ~0x1, speed_hz);

    /*
    * SPI framework set xfer->speed_hz to master->max_speed_hz if
    --
    2.7.4
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