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    Subject[PATCH v3 13/14] arm64: dts: qcom: add sm8150 GPU nodes
    Date
    This brings up the GPU. Tested on HDK855 by running vulkan CTS.

    Signed-off-by: Jonathan Marek <jonathan@marek.ca>
    ---
    arch/arm64/boot/dts/qcom/sm8150.dtsi | 136 +++++++++++++++++++++++++++
    1 file changed, 136 insertions(+)

    diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
    index d117a64f591e..b65fd7027d1e 100644
    --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
    +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
    @@ -10,6 +10,7 @@
    #include <dt-bindings/soc/qcom,rpmh-rsc.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/clock/qcom,gcc-sm8150.h>
    +#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
    #include <dt-bindings/thermal/thermal.h>

    / {
    @@ -549,6 +550,141 @@ glink-edge {
    };
    };

    + gpu: gpu@2c00000 {
    + /*
    + * note: the amd,imageon compatible makes it possible
    + * to use the drm/msm driver without the display node,
    + * make sure to remove it when display node is added
    + */
    + compatible = "qcom,adreno-640.1",
    + "qcom,adreno",
    + "amd,imageon";
    + #stream-id-cells = <16>;
    +
    + reg = <0 0x2c00000 0 0x40000>;
    + reg-names = "kgsl_3d0_reg_memory";
    +
    + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
    +
    + iommus = <&adreno_smmu 0 0x401>;
    +
    + operating-points-v2 = <&gpu_opp_table>;
    +
    + qcom,gmu = <&gmu>;
    +
    + zap-shader {
    + memory-region = <&gpu_mem>;
    + };
    +
    + /* note: downstream checks gpu binning for 675 Mhz */
    + gpu_opp_table: opp-table {
    + compatible = "operating-points-v2";
    +
    + opp-675000000 {
    + opp-hz = /bits/ 64 <675000000>;
    + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
    + };
    +
    + opp-585000000 {
    + opp-hz = /bits/ 64 <585000000>;
    + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
    + };
    +
    + opp-499200000 {
    + opp-hz = /bits/ 64 <499200000>;
    + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
    + };
    +
    + opp-427000000 {
    + opp-hz = /bits/ 64 <427000000>;
    + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
    + };
    +
    + opp-345000000 {
    + opp-hz = /bits/ 64 <345000000>;
    + opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
    + };
    +
    + opp-257000000 {
    + opp-hz = /bits/ 64 <257000000>;
    + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
    + };
    + };
    + };
    +
    + gmu: gmu@2c6a000 {
    + compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
    +
    + reg = <0 0x2c6a000 0 0x30000>,
    + <0 0xb290000 0 0x10000>,
    + <0 0xb490000 0 0x10000>;
    + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
    +
    + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
    + interrupt-names = "hfi", "gmu";
    +
    + clocks = <&gpucc GPU_CC_AHB_CLK>,
    + <&gpucc GPU_CC_CX_GMU_CLK>,
    + <&gpucc GPU_CC_CXO_CLK>,
    + <&gcc GCC_DDRSS_GPU_AXI_CLK>,
    + <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
    + clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
    +
    + power-domains = <&gpucc GPU_CX_GDSC>,
    + <&gpucc GPU_GX_GDSC>;
    + power-domain-names = "cx", "gx";
    +
    + iommus = <&adreno_smmu 5 0x400>;
    +
    + operating-points-v2 = <&gmu_opp_table>;
    +
    + gmu_opp_table: opp-table {
    + compatible = "operating-points-v2";
    +
    + opp-200000000 {
    + opp-hz = /bits/ 64 <200000000>;
    + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
    + };
    + };
    + };
    +
    + gpucc: clock-controller@2c90000 {
    + compatible = "qcom,sm8150-gpucc";
    + reg = <0 0x2c90000 0 0x9000>;
    + clocks = <&rpmhcc RPMH_CXO_CLK>,
    + <&gcc GCC_GPU_GPLL0_CLK_SRC>,
    + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
    + clock-names = "bi_tcxo",
    + "gcc_gpu_gpll0_clk_src",
    + "gcc_gpu_gpll0_div_clk_src";
    + #clock-cells = <1>;
    + #reset-cells = <1>;
    + #power-domain-cells = <1>;
    + };
    +
    + adreno_smmu: iommu@2ca0000 {
    + compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
    + reg = <0 0x2ca0000 0 0x10000>;
    + #iommu-cells = <2>;
    + #global-interrupts = <1>;
    + interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
    + clocks = <&gpucc GPU_CC_AHB_CLK>,
    + <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
    + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
    + clock-names = "ahb", "bus", "iface";
    +
    + power-domains = <&gpucc GPU_CX_GDSC>;
    + };
    +
    tlmm: pinctrl@3100000 {
    compatible = "qcom,sm8150-pinctrl";
    reg = <0x0 0x03100000 0x0 0x300000>,
    --
    2.26.1
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