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    Subject[PATCH v6 10/14] dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC
    Date
    Add host mode dt-bindings for TI's J721E SoC.

    Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
    Reviewed-by: Rob Herring <robh@kernel.org>
    ---
    .../bindings/pci/ti,j721e-pci-host.yaml | 113 ++++++++++++++++++
    1 file changed, 113 insertions(+)
    create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml

    diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
    new file mode 100644
    index 000000000000..d7b60487c6c3
    --- /dev/null
    +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
    @@ -0,0 +1,113 @@
    +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    +# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
    +%YAML 1.2
    +---
    +$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#"
    +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
    +
    +title: TI J721E PCI Host (PCIe Wrapper)
    +
    +maintainers:
    + - Kishon Vijay Abraham I <kishon@ti.com>
    +
    +allOf:
    + - $ref: "cdns-pcie-host.yaml#"
    +
    +properties:
    + compatible:
    + enum:
    + - ti,j721e-pcie-host
    +
    + reg:
    + maxItems: 4
    +
    + reg-names:
    + items:
    + - const: intd_cfg
    + - const: user_cfg
    + - const: reg
    + - const: cfg
    +
    + ti,syscon-pcie-ctrl:
    + description: Phandle to the SYSCON entry required for configuring PCIe mode
    + and link speed.
    + allOf:
    + - $ref: /schemas/types.yaml#/definitions/phandle
    +
    + power-domains:
    + maxItems: 1
    +
    + clocks:
    + maxItems: 1
    + description: clock-specifier to represent input to the PCIe
    +
    + clock-names:
    + items:
    + - const: fck
    +
    + vendor-id:
    + const: 0x104c
    +
    + device-id:
    + const: 0xb00d
    +
    + msi-map: true
    +
    +required:
    + - compatible
    + - reg
    + - reg-names
    + - ti,syscon-pcie-ctrl
    + - max-link-speed
    + - num-lanes
    + - power-domains
    + - clocks
    + - clock-names
    + - vendor-id
    + - device-id
    + - msi-map
    + - dma-coherent
    + - dma-ranges
    + - ranges
    + - reset-gpios
    + - phys
    + - phy-names
    +
    +examples:
    + - |
    + #include <dt-bindings/soc/ti,sci_pm_domain.h>
    + #include <dt-bindings/gpio/gpio.h>
    +
    + bus {
    + #address-cells = <2>;
    + #size-cells = <2>;
    +
    + pcie0_rc: pcie@2900000 {
    + compatible = "ti,j721e-pcie-host";
    + reg = <0x00 0x02900000 0x00 0x1000>,
    + <0x00 0x02907000 0x00 0x400>,
    + <0x00 0x0d000000 0x00 0x00800000>,
    + <0x00 0x10000000 0x00 0x00001000>;
    + reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
    + ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
    + max-link-speed = <3>;
    + num-lanes = <2>;
    + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
    + clocks = <&k3_clks 239 1>;
    + clock-names = "fck";
    + device_type = "pci";
    + #address-cells = <3>;
    + #size-cells = <2>;
    + bus-range = <0x0 0xf>;
    + vendor-id = <0x104c>;
    + device-id = <0xb00d>;
    + msi-map = <0x0 &gic_its 0x0 0x10000>;
    + dma-coherent;
    + reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
    + phys = <&serdes0_pcie_link>;
    + phy-names = "pcie-phy";
    + ranges = <0x01000000 0x0 0x10001000 0x00 0x10001000 0x0 0x0010000>,
    + <0x02000000 0x0 0x10011000 0x00 0x10011000 0x0 0x7fef000>;
    + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
    + };
    + };
    --
    2.17.1
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