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    Subject[PATCH v6 00/14] Add PCIe support to TI's J721E SoC
    Date
    TI's J721E SoC uses Cadence PCIe core to implement both RC mode
    and EP mode.

    The high level features are:
    *) Supports Legacy, MSI and MSI-X interrupt
    *) Supports upto GEN4 speed mode
    *) Supports SR-IOV
    *) Supports multiple physical function
    *) Ability to route all transactions via SMMU

    This patch series
    *) Add support in Cadence PCIe core to be used for TI's J721E SoC
    *) Add a driver for J721E PCIe wrapper

    v1 of the series can be found @ [1]
    v2 of the series can be found @ [2]
    v3 of the series can be found @ [5]
    v4 of the series can be found @ [6]
    v5 of the series can be found @ [7]

    Changes from v5:
    1) Added Reviewed-by: for PATCH #6
    2) Protect writes to PCI_STATUS with spin_lock during raising interrupts
    in EP mode to reduce the time between read and write of RMW.

    Changes from v4:
    1) Added Reviewed-by: & Acked-by: tags from RobH
    2) Removed un-used accessors for pcie-cadence.h and removed having ops
    for read/write accessors
    3) Updated cdns,cdns-pcie-host.yaml to remove "mem" from reg

    Changes from v3:
    1) Changed the order of files in MAINTAINTERS file to fix Joe's comments
    2) Fixed indentation and added Reviewed-by: Rob Herring <robh@kernel.org>
    3) Cleaned up computing msix_tbl
    4) Fixed RobH's comment on J721E driver

    Changes from v2:
    1) Converting Cadence binding to YAML schema was done as a
    separate series [3] & [4]. [3] is merged and [4] is
    pending.
    2) Included MSI-X support in this series
    3) Added link down interrupt handling (only error message)
    4) Rebased to latest 5.7-rc1
    5) Adapted TI J721E binding to [3] & [4]

    Changes from v1:
    1) Added DT schemas cdns-pcie-host.yaml, cdns-pcie-ep.yaml and
    cdns-pcie.yaml for Cadence PCIe core and included it in
    TI's PCIe DT schema.
    2) Added cpu_addr_fixup() for Cadence Platform driver.
    3) Fixed subject/description/renamed functions as commented by
    Andrew Murray.

    [1] -> http://lore.kernel.org/r/20191209092147.22901-1-kishon@ti.com
    [2] -> http://lore.kernel.org/r/20200106102058.19183-1-kishon@ti.com
    [3] -> http://lore.kernel.org/r/20200305103017.16706-1-kishon@ti.com
    [4] -> http://lore.kernel.org/r/20200417114322.31111-1-kishon@ti.com
    [5] -> http://lore.kernel.org/r/20200417125753.13021-1-kishon@ti.com
    [6] -> http://lore.kernel.org/r/20200506151429.12255-1-kishon@ti.com
    [7] -> http://lore.kernel.org/r/20200522033631.32574-1-kishon@ti.com

    Alan Douglas (1):
    PCI: cadence: Add MSI-X support to Endpoint driver

    Kishon Vijay Abraham I (13):
    PCI: cadence: Fix cdns_pcie_{host|ep}_setup() error path
    linux/kernel.h: Add PTR_ALIGN_DOWN macro
    PCI: cadence: Convert all r/w accessors to perform only 32-bit
    accesses
    PCI: cadence: Add support to start link and verify link status
    PCI: cadence: Allow pci_host_bridge to have custom pci_ops
    dt-bindings: PCI: cadence: Remove "mem" from reg binding
    PCI: cadence: Add new *ops* for CPU addr fixup
    PCI: cadence: Fix updating Vendor ID and Subsystem Vendor ID register
    dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC
    dt-bindings: PCI: Add EP mode dt-bindings for TI's J721E SoC
    PCI: j721e: Add TI J721E PCIe driver
    misc: pci_endpoint_test: Add J721E in pci_device_id table
    MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe

    .../bindings/pci/cdns,cdns-pcie-host.yaml | 8 +-
    .../bindings/pci/ti,j721e-pci-ep.yaml | 89 ++++
    .../bindings/pci/ti,j721e-pci-host.yaml | 113 ++++
    MAINTAINERS | 4 +-
    drivers/misc/pci_endpoint_test.c | 9 +
    drivers/pci/controller/cadence/Kconfig | 23 +
    drivers/pci/controller/cadence/Makefile | 1 +
    drivers/pci/controller/cadence/pci-j721e.c | 493 ++++++++++++++++++
    .../pci/controller/cadence/pcie-cadence-ep.c | 129 ++++-
    .../controller/cadence/pcie-cadence-host.c | 59 ++-
    .../controller/cadence/pcie-cadence-plat.c | 13 +
    drivers/pci/controller/cadence/pcie-cadence.c | 8 +-
    drivers/pci/controller/cadence/pcie-cadence.h | 133 ++++-
    include/linux/kernel.h | 1 +
    14 files changed, 1030 insertions(+), 53 deletions(-)
    create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml
    create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
    create mode 100644 drivers/pci/controller/cadence/pci-j721e.c

    --
    2.17.1

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