Messages in this thread | | | From | Andy Lutomirski <> | Date | Fri, 31 Jul 2020 18:28:37 -0700 | Subject | Re: [PATCH v6 12/12] x86/traps: Fix up invalid PASID |
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On Mon, Jul 13, 2020 at 4:48 PM Fenghua Yu <fenghua.yu@intel.com> wrote: > > A #GP fault is generated when ENQCMD instruction is executed without > a valid PASID value programmed in the current thread's PASID MSR. The > #GP fault handler will initialize the MSR if a PASID has been allocated > for this process.
Let's take a step back here. Why are we trying to avoid IPIs? If you call munmap(), you IPI other CPUs running tasks in the current mm. If you do perf_event_open() and thus acquire RDPMC permission, you IPI other CPUs running tasks in the current mm. If you call modify_ldt(), you IPI other CPUs running tasks in the current mm. These events can all happen more than once per process.
Now we have ENQCMD. An mm can be assigned a PASID *once* in the model that these patches support. Why not just send an IPI using essentially identical code to the LDT sync or the CR4.PCE sync?
--Andy
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