Messages in this thread | | | Subject | Re: [PATCH 2/2] ASoC: Intel: Add period size constraint on strago board | From | Pierre-Louis Bossart <> | Date | Wed, 29 Jul 2020 09:08:38 -0500 |
| |
On 7/29/20 6:03 AM, Brent Lu wrote: > From: Yu-Hsuan Hsu <yuhsuan@chromium.org> > > The CRAS server does not set the period size in hw_param so ALSA will > calculate a value for period size which is based on the buffer size > and other parameters. The value may not always be aligned with Atom's > dsp design so a constraint is added to make sure the board always has > a good value. > > Cyan uses chtmax98090 and others(banon, celes, edgar, kefka...) use > rt5650.
Is this patch required if you've already constrained the period sizes for the platform driver in patch1?
| |