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    Subject[PATCH 5.4 078/138] spi: mediatek: use correct SPI_CFG2_REG MACRO
    Date
    From: leilk.liu <leilk.liu@mediatek.com>

    [ Upstream commit 44b37eb79e16a56cb30ba55b2da452396b941e7a ]

    this patch use correct SPI_CFG2_REG offset.

    Signed-off-by: leilk.liu <leilk.liu@mediatek.com>
    Link: https://lore.kernel.org/r/20200701090020.7935-1-leilk.liu@mediatek.com
    Signed-off-by: Mark Brown <broonie@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/spi/spi-mt65xx.c | 15 ++++++++-------
    1 file changed, 8 insertions(+), 7 deletions(-)

    diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c
    index 6888a4dcff6de..8acf24f7c5d40 100644
    --- a/drivers/spi/spi-mt65xx.c
    +++ b/drivers/spi/spi-mt65xx.c
    @@ -36,7 +36,6 @@
    #define SPI_CFG0_SCK_LOW_OFFSET 8
    #define SPI_CFG0_CS_HOLD_OFFSET 16
    #define SPI_CFG0_CS_SETUP_OFFSET 24
    -#define SPI_ADJUST_CFG0_SCK_LOW_OFFSET 16
    #define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0
    #define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16

    @@ -48,6 +47,8 @@
    #define SPI_CFG1_CS_IDLE_MASK 0xff
    #define SPI_CFG1_PACKET_LOOP_MASK 0xff00
    #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
    +#define SPI_CFG2_SCK_HIGH_OFFSET 0
    +#define SPI_CFG2_SCK_LOW_OFFSET 16

    #define SPI_CMD_ACT BIT(0)
    #define SPI_CMD_RESUME BIT(1)
    @@ -279,7 +280,7 @@ static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
    static void mtk_spi_prepare_transfer(struct spi_master *master,
    struct spi_transfer *xfer)
    {
    - u32 spi_clk_hz, div, sck_time, cs_time, reg_val = 0;
    + u32 spi_clk_hz, div, sck_time, cs_time, reg_val;
    struct mtk_spi *mdata = spi_master_get_devdata(master);

    spi_clk_hz = clk_get_rate(mdata->spi_clk);
    @@ -292,18 +293,18 @@ static void mtk_spi_prepare_transfer(struct spi_master *master,
    cs_time = sck_time * 2;

    if (mdata->dev_comp->enhance_timing) {
    + reg_val = (((sck_time - 1) & 0xffff)
    + << SPI_CFG2_SCK_HIGH_OFFSET);
    reg_val |= (((sck_time - 1) & 0xffff)
    - << SPI_CFG0_SCK_HIGH_OFFSET);
    - reg_val |= (((sck_time - 1) & 0xffff)
    - << SPI_ADJUST_CFG0_SCK_LOW_OFFSET);
    + << SPI_CFG2_SCK_LOW_OFFSET);
    writel(reg_val, mdata->base + SPI_CFG2_REG);
    - reg_val |= (((cs_time - 1) & 0xffff)
    + reg_val = (((cs_time - 1) & 0xffff)
    << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
    reg_val |= (((cs_time - 1) & 0xffff)
    << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
    writel(reg_val, mdata->base + SPI_CFG0_REG);
    } else {
    - reg_val |= (((sck_time - 1) & 0xff)
    + reg_val = (((sck_time - 1) & 0xff)
    << SPI_CFG0_SCK_HIGH_OFFSET);
    reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
    reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
    --
    2.25.1


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