| Subject | Re: [PATCH v2 06/18] clk: at91: sam9x60-pll: use frac when setting frequency | From | Stephen Boyd <> | Date | Fri, 24 Jul 2020 02:21:14 -0700 |
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Quoting Claudiu Beznea (2020-07-22 00:38:14) > In commit a436c2a447e59 ("clk: at91: add sam9x60 PLL driver") > the fractional part of PLL wasn't set on registers but it was > calculated and taken into account for determining div and mul > (see sam9x60_pll_get_best_div_mul()). > > Fixes: a436c2a447e59 ("clk: at91: add sam9x60 PLL driver") > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > ---
Applied to clk-next
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