Messages in this thread | | | Date | Wed, 22 Jul 2020 13:48:22 +0530 | From | Srikar Dronamraju <> | Subject | Re: [PATCH v2 06/10] powerpc/smp: Generalize 2nd sched domain |
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* peterz@infradead.org <peterz@infradead.org> [2020-07-22 09:46:24]:
> On Tue, Jul 21, 2020 at 05:08:10PM +0530, Srikar Dronamraju wrote: > > Currently "CACHE" domain happens to be the 2nd sched domain as per > > powerpc_topology. This domain will collapse if cpumask of l2-cache is > > same as SMT domain. However we could generalize this domain such that it > > could mean either be a "CACHE" domain or a "BIGCORE" domain. > > What's the whole smallcore vs bigcore thing? > > Would it make sense to have an actual overview of the various topology > layers somewhere? Because I'm getting lost and can't really make sense > of the code due to that.
To quote with an example: using (Power 9)
Power 9 is an SMT 8 core by design. However this 8 thread core can run as 2 independent core with threads 0,2,4 and 6 acting like a core, while threads 1,3,5,7 acting as another core.
The firmware can decide to showcase them as 2 independent small cores or as one big core. However the LLC (i.e last level of cache) is shared between all the threads of the SMT 8 core. Future power chips, LLC might change, it may be expanded to share with another SMT 8 core or it could be made specific to SMT 4 core.
The smt 8 core is also known as fused core/ Big core. The smaller smt 4 core is known as small core.
So on a Power9 Baremetal, the firmware would show up as SMT4 core. and we have a CACHE level at SMT 8. CACHE level would be very very similar to MC domain in X86.
Hope this is clear.
-- Thanks and Regards Srikar Dronamraju
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