Messages in this thread | | | Date | Tue, 21 Jul 2020 21:20:02 +0200 | From | Peter Zijlstra <> | Subject | Re: [PATCH V6 09/14] perf/x86/intel: Support TopDown metrics on Ice Lake |
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On Tue, Jul 21, 2020 at 10:38:59AM -0700, Andi Kleen wrote: > > Also, that for_each_set_bit() loop, trying to find the events to > > update... > > > > Can't we, instead, make the SLOTS update advance 5 running counters in > > cpuc and feed the events off of that? > > The original patches implemented this through a perf transaction and a > cache. I think what you're suggesting is similar to the old cache.
I can't remember :-) Anyway, the TXN_READ thing Kan pointed out should work fine, I just missed it when reading through the code.
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