Messages in this thread | | | Subject | Re: [PATCH V6 03/14] perf/x86/intel: Introduce the fourth fixed counter | From | "Liang, Kan" <> | Date | Mon, 20 Jul 2020 14:22:27 -0400 |
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On 7/20/2020 12:20 PM, Peter Zijlstra wrote: > On Fri, Jul 17, 2020 at 07:05:43AM -0700, kan.liang@linux.intel.com wrote: >> /* >> + * There is no event-code assigned to the fixed-mode PMCs. >> + * >> + * For a fixed-mode PMC, which has an equivalent event on a general-purpose >> + * PMC, the event-code of the equivalent event is used for the fixed-mode PMC, >> + * e.g., Instr_Retired.Any and CPU_CLK_Unhalted.Core. >> + * >> + * For a fixed-mode PMC, which doesn't have an equivalent event, a >> + * pseudo-encoding is used, e.g., CPU_CLK_Unhalted.Ref and TOPDOWN.SLOTS. >> + * The pseudo event-code for a fixed-mode PMC must be 0x00. >> + * The pseudo umask-code is 0x0X. The X indicates the index of the fixed >> + * counter. > > Isn't it X+1 ? Such that 0x0000 is an invalid event? After all, the > pseudo event for Fixed2 is 0x0300.
I will fix the inaccurate description as below in V7.
+ * The pseudo umask-code is 0xX. The X equals the index of the fixed + * counter + 1, e.g., the fixed counter 2 has the pseudo-encoding 0x0300.
Thanks, Kan
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