Messages in this thread | | | Subject | Re: [PATCH V5 1/4] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR0 register | From | Suzuki K Poulose <> | Date | Thu, 2 Jul 2020 12:22:42 +0100 |
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On 05/27/2020 04:03 AM, Anshuman Khandual wrote: > Enable EVC, FGT, EXS features bits in ID_AA64MMFR0 register as per ARM DDI > 0487F.a specification. > > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: Suzuki K Poulose <suzuki.poulose@arm.com> > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Suggested-by: Will Deacon <will@kernel.org> > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> > --- > arch/arm64/include/asm/sysreg.h | 3 +++ > arch/arm64/kernel/cpufeature.c | 3 +++ > 2 files changed, 6 insertions(+) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index fa9d02ca4b25..cf983d03aa4c 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -703,6 +703,9 @@ > #define ID_AA64ZFR0_SVEVER_SVE2 0x1 > > /* id_aa64mmfr0 */ > +#define ID_AA64MMFR0_ECV_SHIFT 60 > +#define ID_AA64MMFR0_FGT_SHIFT 56 > +#define ID_AA64MMFR0_EXS_SHIFT 44 > #define ID_AA64MMFR0_TGRAN4_SHIFT 28 > #define ID_AA64MMFR0_TGRAN64_SHIFT 24 > #define ID_AA64MMFR0_TGRAN16_SHIFT 20 > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index ada9f6f9b0f6..feaa6dcd6f7b 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -267,6 +267,9 @@ static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { > }; > > static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0),
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
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