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    Subject[PATCH v2 net-next 02/14] qed: reformat public_port::transceiver_data a bit
    Date
    Prior to adding new bitfields, reformat the existing ones from spaces
    to tabs, and unify all hex values to lowercase.

    Signed-off-by: Alexander Lobakin <alobakin@marvell.com>
    Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
    ---
    drivers/net/ethernet/qlogic/qed/qed_hsi.h | 108 +++++++++++-----------
    1 file changed, 55 insertions(+), 53 deletions(-)

    diff --git a/drivers/net/ethernet/qlogic/qed/qed_hsi.h b/drivers/net/ethernet/qlogic/qed/qed_hsi.h
    index 6bb0bbc0013b..0d0a109d94b4 100644
    --- a/drivers/net/ethernet/qlogic/qed/qed_hsi.h
    +++ b/drivers/net/ethernet/qlogic/qed/qed_hsi.h
    @@ -11973,59 +11973,61 @@ struct public_port {
    struct dcbx_mib operational_dcbx_mib;

    u32 reserved[2];
    - u32 transceiver_data;
    -#define ETH_TRANSCEIVER_STATE_MASK 0x000000FF
    -#define ETH_TRANSCEIVER_STATE_SHIFT 0x00000000
    -#define ETH_TRANSCEIVER_STATE_OFFSET 0x00000000
    -#define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000
    -#define ETH_TRANSCEIVER_STATE_PRESENT 0x00000001
    -#define ETH_TRANSCEIVER_STATE_VALID 0x00000003
    -#define ETH_TRANSCEIVER_STATE_UPDATING 0x00000008
    -#define ETH_TRANSCEIVER_TYPE_MASK 0x0000FF00
    -#define ETH_TRANSCEIVER_TYPE_OFFSET 0x8
    -#define ETH_TRANSCEIVER_TYPE_NONE 0x00
    -#define ETH_TRANSCEIVER_TYPE_UNKNOWN 0xFF
    -#define ETH_TRANSCEIVER_TYPE_1G_PCC 0x01
    -#define ETH_TRANSCEIVER_TYPE_1G_ACC 0x02
    -#define ETH_TRANSCEIVER_TYPE_1G_LX 0x03
    -#define ETH_TRANSCEIVER_TYPE_1G_SX 0x04
    -#define ETH_TRANSCEIVER_TYPE_10G_SR 0x05
    -#define ETH_TRANSCEIVER_TYPE_10G_LR 0x06
    -#define ETH_TRANSCEIVER_TYPE_10G_LRM 0x07
    -#define ETH_TRANSCEIVER_TYPE_10G_ER 0x08
    -#define ETH_TRANSCEIVER_TYPE_10G_PCC 0x09
    -#define ETH_TRANSCEIVER_TYPE_10G_ACC 0x0a
    -#define ETH_TRANSCEIVER_TYPE_XLPPI 0x0b
    -#define ETH_TRANSCEIVER_TYPE_40G_LR4 0x0c
    -#define ETH_TRANSCEIVER_TYPE_40G_SR4 0x0d
    -#define ETH_TRANSCEIVER_TYPE_40G_CR4 0x0e
    -#define ETH_TRANSCEIVER_TYPE_100G_AOC 0x0f
    -#define ETH_TRANSCEIVER_TYPE_100G_SR4 0x10
    -#define ETH_TRANSCEIVER_TYPE_100G_LR4 0x11
    -#define ETH_TRANSCEIVER_TYPE_100G_ER4 0x12
    -#define ETH_TRANSCEIVER_TYPE_100G_ACC 0x13
    -#define ETH_TRANSCEIVER_TYPE_100G_CR4 0x14
    -#define ETH_TRANSCEIVER_TYPE_4x10G_SR 0x15
    -#define ETH_TRANSCEIVER_TYPE_25G_CA_N 0x16
    -#define ETH_TRANSCEIVER_TYPE_25G_ACC_S 0x17
    -#define ETH_TRANSCEIVER_TYPE_25G_CA_S 0x18
    -#define ETH_TRANSCEIVER_TYPE_25G_ACC_M 0x19
    -#define ETH_TRANSCEIVER_TYPE_25G_CA_L 0x1a
    -#define ETH_TRANSCEIVER_TYPE_25G_ACC_L 0x1b
    -#define ETH_TRANSCEIVER_TYPE_25G_SR 0x1c
    -#define ETH_TRANSCEIVER_TYPE_25G_LR 0x1d
    -#define ETH_TRANSCEIVER_TYPE_25G_AOC 0x1e
    -#define ETH_TRANSCEIVER_TYPE_4x10G 0x1f
    -#define ETH_TRANSCEIVER_TYPE_4x25G_CR 0x20
    -#define ETH_TRANSCEIVER_TYPE_1000BASET 0x21
    -#define ETH_TRANSCEIVER_TYPE_10G_BASET 0x22
    -#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR 0x30
    -#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR 0x31
    -#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR 0x32
    -#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR 0x33
    -#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR 0x34
    -#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR 0x35
    -#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC 0x36
    +
    + u32 transceiver_data;
    +#define ETH_TRANSCEIVER_STATE_MASK 0x000000ff
    +#define ETH_TRANSCEIVER_STATE_SHIFT 0x00000000
    +#define ETH_TRANSCEIVER_STATE_OFFSET 0x00000000
    +#define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000
    +#define ETH_TRANSCEIVER_STATE_PRESENT 0x00000001
    +#define ETH_TRANSCEIVER_STATE_VALID 0x00000003
    +#define ETH_TRANSCEIVER_STATE_UPDATING 0x00000008
    +#define ETH_TRANSCEIVER_TYPE_MASK 0x0000ff00
    +#define ETH_TRANSCEIVER_TYPE_OFFSET 0x8
    +#define ETH_TRANSCEIVER_TYPE_NONE 0x00
    +#define ETH_TRANSCEIVER_TYPE_UNKNOWN 0xff
    +#define ETH_TRANSCEIVER_TYPE_1G_PCC 0x01
    +#define ETH_TRANSCEIVER_TYPE_1G_ACC 0x02
    +#define ETH_TRANSCEIVER_TYPE_1G_LX 0x03
    +#define ETH_TRANSCEIVER_TYPE_1G_SX 0x04
    +#define ETH_TRANSCEIVER_TYPE_10G_SR 0x05
    +#define ETH_TRANSCEIVER_TYPE_10G_LR 0x06
    +#define ETH_TRANSCEIVER_TYPE_10G_LRM 0x07
    +#define ETH_TRANSCEIVER_TYPE_10G_ER 0x08
    +#define ETH_TRANSCEIVER_TYPE_10G_PCC 0x09
    +#define ETH_TRANSCEIVER_TYPE_10G_ACC 0x0a
    +#define ETH_TRANSCEIVER_TYPE_XLPPI 0x0b
    +#define ETH_TRANSCEIVER_TYPE_40G_LR4 0x0c
    +#define ETH_TRANSCEIVER_TYPE_40G_SR4 0x0d
    +#define ETH_TRANSCEIVER_TYPE_40G_CR4 0x0e
    +#define ETH_TRANSCEIVER_TYPE_100G_AOC 0x0f
    +#define ETH_TRANSCEIVER_TYPE_100G_SR4 0x10
    +#define ETH_TRANSCEIVER_TYPE_100G_LR4 0x11
    +#define ETH_TRANSCEIVER_TYPE_100G_ER4 0x12
    +#define ETH_TRANSCEIVER_TYPE_100G_ACC 0x13
    +#define ETH_TRANSCEIVER_TYPE_100G_CR4 0x14
    +#define ETH_TRANSCEIVER_TYPE_4x10G_SR 0x15
    +#define ETH_TRANSCEIVER_TYPE_25G_CA_N 0x16
    +#define ETH_TRANSCEIVER_TYPE_25G_ACC_S 0x17
    +#define ETH_TRANSCEIVER_TYPE_25G_CA_S 0x18
    +#define ETH_TRANSCEIVER_TYPE_25G_ACC_M 0x19
    +#define ETH_TRANSCEIVER_TYPE_25G_CA_L 0x1a
    +#define ETH_TRANSCEIVER_TYPE_25G_ACC_L 0x1b
    +#define ETH_TRANSCEIVER_TYPE_25G_SR 0x1c
    +#define ETH_TRANSCEIVER_TYPE_25G_LR 0x1d
    +#define ETH_TRANSCEIVER_TYPE_25G_AOC 0x1e
    +#define ETH_TRANSCEIVER_TYPE_4x10G 0x1f
    +#define ETH_TRANSCEIVER_TYPE_4x25G_CR 0x20
    +#define ETH_TRANSCEIVER_TYPE_1000BASET 0x21
    +#define ETH_TRANSCEIVER_TYPE_10G_BASET 0x22
    +#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR 0x30
    +#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR 0x31
    +#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR 0x32
    +#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR 0x33
    +#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR 0x34
    +#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR 0x35
    +#define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC 0x36
    +
    u32 wol_info;
    u32 wol_pkt_len;
    u32 wol_pkt_details;
    --
    2.25.1
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      Last update: 2020-07-19 22:16    [W:6.642 / U:0.072 seconds]
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