Messages in this thread | | | From | Anup Patel <> | Date | Thu, 16 Jul 2020 18:43:03 +0530 | Subject | Re: [PATCH] riscv: Add SiFive drivers to rv32_defconfig |
| |
On Thu, Jul 16, 2020 at 10:10 AM Bin Meng <bmeng.cn@gmail.com> wrote: > > From: Bin Meng <bin.meng@windriver.com> > > This adds SiFive drivers to rv32_defconfig, to keep in sync with the > 64-bit config. This is useful when testing 32-bit kernel with QEMU > 'sifive_u' 32-bit machine. > > Signed-off-by: Bin Meng <bin.meng@windriver.com> > --- > > arch/riscv/configs/rv32_defconfig | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig > index 05bbf52..8759501 100644 > --- a/arch/riscv/configs/rv32_defconfig > +++ b/arch/riscv/configs/rv32_defconfig > @@ -14,6 +14,7 @@ CONFIG_CHECKPOINT_RESTORE=y > CONFIG_BLK_DEV_INITRD=y > CONFIG_EXPERT=y > CONFIG_BPF_SYSCALL=y > +CONFIG_SOC_SIFIVE=y > CONFIG_SOC_VIRT=y > CONFIG_ARCH_RV32I=y > CONFIG_SMP=y > @@ -61,6 +62,8 @@ CONFIG_HVC_RISCV_SBI=y > CONFIG_VIRTIO_CONSOLE=y > CONFIG_HW_RANDOM=y > CONFIG_HW_RANDOM_VIRTIO=y > +CONFIG_SPI=y > +CONFIG_SPI_SIFIVE=y > # CONFIG_PTP_1588_CLOCK is not set > CONFIG_POWER_RESET=y > CONFIG_DRM=y > @@ -76,6 +79,8 @@ CONFIG_USB_OHCI_HCD=y > CONFIG_USB_OHCI_HCD_PLATFORM=y > CONFIG_USB_STORAGE=y > CONFIG_USB_UAS=y > +CONFIG_MMC=y > +CONFIG_MMC_SPI=y > CONFIG_RTC_CLASS=y > CONFIG_VIRTIO_PCI=y > CONFIG_VIRTIO_BALLOON=y > -- > 2.7.4 >
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards, Anup
| |