lkml.org 
[lkml]   [2020]   [Jul]   [14]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: [RFC PATCH 04/15] x86/pks: Preserve the PKRS MSR on context switch
On Tue, Jul 14, 2020 at 09:05:39PM +0200, Peter Zijlstra wrote:
> On Tue, Jul 14, 2020 at 11:53:22AM -0700, Ira Weiny wrote:
> > On Tue, Jul 14, 2020 at 10:27:01AM +0200, Peter Zijlstra wrote:
> > > On Tue, Jul 14, 2020 at 12:02:09AM -0700, ira.weiny@intel.com wrote:
> > > > From: Ira Weiny <ira.weiny@intel.com>
> > > >
> > > > The PKRS MSR is defined as a per-core register. This isolates memory
> > > > access by CPU. Unfortunately, the MSR is not preserved by XSAVE.
> > > > Therefore, We must preserve the protections for individual tasks even if
> > > > they are context switched out and placed on another cpu later.
> > >
> > > This is a contradiction and utter trainwreck.
> >
> > I don't understand where there is a contradiction? Perhaps I should have said
> > the MSR is not XSAVE managed vs 'preserved'?
>
> You're stating the MSR is per-*CORE*, and then continue to talk about
> per-task state.
>
> We've had a bunch of MSRs have exactly that problem recently, and it's
> not fun. We're not going to do that again.

Ah sorry, my mistake yes I meant 'per-logical-processor' like Dave said. I'll
update the commit message.

Ira

\
 
 \ /
  Last update: 2020-07-14 21:11    [W:1.835 / U:0.328 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site