lkml.org 
[lkml]   [2020]   [Jul]   [13]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH 5/9] arm64: dts: renesas: r8a774e1: Add SYS-DMAC device nodes
    Date
    From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>

    Add sys-dmac[0-2] device nodes for RZ/G2H (R8A774E1) SoC.

    Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
    Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
    ---
    arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 126 ++++++++++++++++++++++
    1 file changed, 126 insertions(+)

    diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
    index 0fc0d9ff5bc5..9e05d134a295 100644
    --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
    +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
    @@ -408,6 +408,132 @@
    /* placeholder */
    };

    + dmac0: dma-controller@e6700000 {
    + compatible = "renesas,dmac-r8a774e1",
    + "renesas,rcar-dmac";
    + reg = <0 0xe6700000 0 0x10000>;
    + interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
    + interrupt-names = "error",
    + "ch0", "ch1", "ch2", "ch3",
    + "ch4", "ch5", "ch6", "ch7",
    + "ch8", "ch9", "ch10", "ch11",
    + "ch12", "ch13", "ch14", "ch15";
    + clocks = <&cpg CPG_MOD 219>;
    + clock-names = "fck";
    + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
    + resets = <&cpg 219>;
    + #dma-cells = <1>;
    + dma-channels = <16>;
    + iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
    + <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
    + <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
    + <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
    + <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
    + <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
    + <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
    + <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
    + };
    +
    + dmac1: dma-controller@e7300000 {
    + compatible = "renesas,dmac-r8a774e1",
    + "renesas,rcar-dmac";
    + reg = <0 0xe7300000 0 0x10000>;
    + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
    + interrupt-names = "error",
    + "ch0", "ch1", "ch2", "ch3",
    + "ch4", "ch5", "ch6", "ch7",
    + "ch8", "ch9", "ch10", "ch11",
    + "ch12", "ch13", "ch14", "ch15";
    + clocks = <&cpg CPG_MOD 218>;
    + clock-names = "fck";
    + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
    + resets = <&cpg 218>;
    + #dma-cells = <1>;
    + dma-channels = <16>;
    + iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
    + <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
    + <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
    + <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
    + <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
    + <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
    + <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
    + <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
    + };
    +
    + dmac2: dma-controller@e7310000 {
    + compatible = "renesas,dmac-r8a774e1",
    + "renesas,rcar-dmac";
    + reg = <0 0xe7310000 0 0x10000>;
    + interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
    + interrupt-names = "error",
    + "ch0", "ch1", "ch2", "ch3",
    + "ch4", "ch5", "ch6", "ch7",
    + "ch8", "ch9", "ch10", "ch11",
    + "ch12", "ch13", "ch14", "ch15";
    + clocks = <&cpg CPG_MOD 217>;
    + clock-names = "fck";
    + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
    + resets = <&cpg 217>;
    + #dma-cells = <1>;
    + dma-channels = <16>;
    + iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
    + <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
    + <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
    + <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
    + <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
    + <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
    + <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
    + <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
    + };
    +
    ipmmu_ds0: iommu@e6740000 {
    compatible = "renesas,ipmmu-r8a774e1";
    reg = <0 0xe6740000 0 0x1000>;
    --
    2.17.1
    \
     
     \ /
      Last update: 2020-07-13 23:36    [W:2.572 / U:0.128 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site