Messages in this thread | | | Date | Fri, 10 Jul 2020 20:28:01 -0400 | From | Sasha Levin <> | Subject | Re: [PATCH stable v4.9 v2] arm64: entry: Place an SB sequence following an ERET instruction |
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On Thu, Jul 09, 2020 at 12:50:23PM -0700, Florian Fainelli wrote: >From: Will Deacon <will.deacon@arm.com> > >commit 679db70801da9fda91d26caf13bf5b5ccc74e8e8 upstream > >Some CPUs can speculate past an ERET instruction and potentially perform >speculative accesses to memory before processing the exception return. >Since the register state is often controlled by a lower privilege level >at the point of an ERET, this could potentially be used as part of a >side-channel attack. > >This patch emits an SB sequence after each ERET so that speculation is >held up on exception return. > >Signed-off-by: Will Deacon <will.deacon@arm.com> >[florian: Adjust hyp-entry.S to account for the label > added change to hyp/entry.S] >Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
I've queued it up, thanks!
-- Thanks, Sasha
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