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    Subject[PATCH v6 5/8] arm64: dts: rockchip: Add nfc dts for PX30 SOC
    Date
    Add nfc(nand flash controller) node for PX30 Soc.

    Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
    ---

    Changes in v6: None
    Changes in v5: None
    Changes in v4: None
    Changes in v3: None
    Changes in v2: None

    arch/arm64/boot/dts/rockchip/px30.dtsi | 15 +++++++++++++++
    1 file changed, 15 insertions(+)

    diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
    index f809dd6d5dc3..261f2f34f42c 100644
    --- a/arch/arm64/boot/dts/rockchip/px30.dtsi
    +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
    @@ -969,6 +969,21 @@
    status = "disabled";
    };

    + nfc: nand-controller@ff3b0000 {
    + compatible = "rockchip,px30-nfc";
    + reg = <0x0 0xff3b0000 0x0 0x4000>;
    + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
    + clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
    + clock-names = "ahb", "nfc";
    + assigned-clocks = <&cru SCLK_NANDC>;
    + assigned-clock-rates = <150000000>;
    + pinctrl-names = "default";
    + pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
    + &flash_rdn &flash_rdy &flash_wrn &flash_dqs>;
    + power-domains = <&power PX30_PD_MMC_NAND>;
    + status = "disabled";
    + };
    +
    gpu: gpu@ff400000 {
    compatible = "rockchip,px30-mali", "arm,mali-bifrost";
    reg = <0x0 0xff400000 0x0 0x4000>;
    --
    2.17.1


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