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    Subject[PATCH AUTOSEL 5.6 266/606] drm/amd/powerplay: perform PG ungate prior to CG ungate
    Date
    From: Evan Quan <evan.quan@amd.com>

    [ Upstream commit f4fcfa4282c1a1bf51475ebb0ffda623eebf1191 ]

    Since gfxoff should be disabled first before trying to access those
    GC registers.

    Signed-off-by: Evan Quan <evan.quan@amd.com>
    Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 6 +++---
    drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 6 +++---
    2 files changed, 6 insertions(+), 6 deletions(-)

    diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
    index e4e5a53b2b4e..8e2acb4df860 100644
    --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
    +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
    @@ -319,12 +319,12 @@ static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr,
    if (*level & profile_mode_mask) {
    hwmgr->saved_dpm_level = hwmgr->dpm_level;
    hwmgr->en_umd_pstate = true;
    - amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
    - AMD_IP_BLOCK_TYPE_GFX,
    - AMD_CG_STATE_UNGATE);
    amdgpu_device_ip_set_powergating_state(hwmgr->adev,
    AMD_IP_BLOCK_TYPE_GFX,
    AMD_PG_STATE_UNGATE);
    + amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
    + AMD_IP_BLOCK_TYPE_GFX,
    + AMD_CG_STATE_UNGATE);
    }
    } else {
    /* exit umd pstate, restore level, enable gfx cg*/
    diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
    index 96e81c7bc266..e2565967db07 100644
    --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
    +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
    @@ -1675,12 +1675,12 @@ static int smu_enable_umd_pstate(void *handle,
    if (*level & profile_mode_mask) {
    smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
    smu_dpm_ctx->enable_umd_pstate = true;
    - amdgpu_device_ip_set_clockgating_state(smu->adev,
    - AMD_IP_BLOCK_TYPE_GFX,
    - AMD_CG_STATE_UNGATE);
    amdgpu_device_ip_set_powergating_state(smu->adev,
    AMD_IP_BLOCK_TYPE_GFX,
    AMD_PG_STATE_UNGATE);
    + amdgpu_device_ip_set_clockgating_state(smu->adev,
    + AMD_IP_BLOCK_TYPE_GFX,
    + AMD_CG_STATE_UNGATE);
    }
    } else {
    /* exit umd pstate, restore level, enable gfx cg*/
    --
    2.25.1
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